Method for manufacturing a stacked capacitor DRAM semiconductor device
US5175121A · kind A · utility
10Cited by
6References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 1991 |
| Grant date | Dec 29, 1992 |
| Priority date | — |
| Expiry date | Aug 29, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor device includes forming contact holes in insulating layers to expose an impurity doped region of a semiconductor substrate. An epitaxial layer is then grown in the contact hole. A polycrystalline silicon layer is formed over the top to provide the lower electrode of a capacitor. Accordingly, the polycrystalline layer is separated from the impurity doped region thereby preventing current leakage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.