Digital signal processor architecture with plural multiply/accumulate devices
US5175702A · kind A · utility
89Cited by
3References
5Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 22, 1991 |
| Grant date | Dec 29, 1992 |
| Priority date | — |
| Expiry date | Jan 22, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5443
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved digital signal processor (DSP) architecture includes several multiply/accumulate devices (M-Unit 0-K) connected to the DSP bus through a delay line and elements for simultaneously operating the multiply/accumulate devices and a device for selectively storing accumulated values into a pre-assigned Dual-Port Randomly Accessible Memory area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.