Processor static mode disable circuit
US5175751A · kind A · utility
5Cited by
6References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 11, 1991 |
| Grant date | Dec 29, 1992 |
| Priority date | — |
| Expiry date | Oct 11, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/19
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input to the control unit of a microprocessor places the microprocessor in a WAIT condition whenever the input clock frequency is determined to be less than a predetermined minimum value. A timing circuit which includes a relatively high capacitance device generates a "kill" signal whenever the time interval between successive clock pulses is greater than a value corresponding to a cut-off frequency. The kill signal is applied to the control unit of the microprocessor and cannot be reset except with a system reset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.