Cascadable parallel to serial converter using tap shift registers and data shift registers while receiving input data from FIFO buffer
US5175819A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 1990 |
| Grant date | Dec 29, 1992 |
| Priority date | — |
| Expiry date | Mar 28, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A parallel-to-serial FIFO buffer device (100) employs a FIFO buffer (110) for storing words of data; a tap-shift-register portion (112); and a data-shift-register portion (116) for converting from parallel to serial format words of data stored in the FIFO buffer (110), tap-shift-register portion (112) controls the conversion process, receives (150) a serial-input-expansion (RSIX) input signal, and develops (170) a serial-output-expansion (RSOX) output signal. The serial-input-expansion input signal (150) and the serial-output-expansion output signal (170) permit the device (100) to be connected with one, or more, similar, device(s) for word length and/or depth expansion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.