Delayed cache write enable circuit for a dual bus microcomputer system with an 80386 and 82385
US5175826A · kind A · utility
19Cited by
14References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 26, 1988 |
| Grant date | Dec 29, 1992 |
| Priority date | — |
| Expiry date | May 26, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an 80386/82385 microcomputer system, the timing requirements placed on non-cache memory components by the 82385 are more stringent than the timing requirements placed on the non-cache memory components by the 80386. The present invention operates on the 82385 cache write enable (CWE) signals, and delays those signals in the event of a read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cache memory components and at the same time does not impact wait state parameters for read miss operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.