Method and apparatus for bus lock during atomic computer operations
US5175829A · kind A · utility
84Cited by
6References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 25, 1988 |
| Grant date | Dec 29, 1992 |
| Priority date | — |
| Expiry date | Oct 25, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system having a plurality of processors sharing common memory and data bus structures and operable to perform atomic operations which comprise several instruction actions, wherein the processor performing the atomic operation prevents memory access interruptions by other processors by locking out other processors during the atomic operation. The system bus includes signal paths accommodating bus lock request and bus lock signals which are provided and received by each processor, which signals are initiated by specific bus lock and lock release instructions added to each processor instruction set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.