Modular memory employing varying number of imput shift register stages
US5175832A · kind A · utility
4Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 23, 1989 |
| Grant date | Dec 29, 1992 |
| Priority date | — |
| Expiry date | May 23, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory including several modules with each module receiving at the input requests coming from a processor and furnishing at the output the responses to these requests. The requests are transmitted to the input of each module via an input shift register. The responses coming from a module are transmitted to the input of a processor via an output shift register. The number of stages of the input shift register is different for each of the modules and the total number of stages for the input and output shift registers associated with one of the modules is constant and independent of the module in question.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.