Multi-mode DRAM controller
US5175835A · kind A · utility
56Cited by
14References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 10, 1990 |
| Grant date | Dec 29, 1992 |
| Priority date | — |
| Expiry date | Jan 10, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0623
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a novel multi-mode DRAM controller adaptd to access DRAM chips of a main storage unit of different size and of different mode types. The novel DRAM controller comprises new address generation and control logic for delaying the RAS and CAS control signals to memory and for expanding the number of address bits employed to address memory chips having a greater number of addresses by at least one address bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.