Microcomputer having a PROM including data security and test circuitry
US5175840A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 1991 |
| Grant date | Dec 29, 1992 |
| Priority date | — |
| Expiry date | Jun 21, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1433
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Easy testability and data security of an electrically erasable programmable read only memory (EEPROM) can be accomplished by disposing pads and an input/output (I/O) circuit providing addresses, data and control signals necessary for the EEPROM test on a semiconductor substrate and by disposing a two-level test I/O interception circuit consisting of an EEPROM device on the substrate such that once the testing is completed, unauthorized accessing is prevented from outside the semiconductor substrate as a result of having a built-in data security function. A microcomputer having this capability is provided with a central processing unit (CPU) for processing data, a memory, such as an EEPROM, which is internally communicating through a common bus (which transmits data, address and control signals) with the CPU, other than during a test mode, and first and second inhibition circuits which provide the security. The first inhibition circuit is coupled to the data bus and provides a first inhibition operation to prevent access operations to the memory. The first inhibition circuit release the first inhibiting operation in accordance with a signal from outside the semiconductor substrate o…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.