Computer-aided design method for restructuring computational networks to minimize shimming delays
US5175843A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1989 |
| Grant date | Dec 29, 1992 |
| Priority date | — |
| Expiry date | Oct 30, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-aided design method for restructuring computational networks to minimize latency and shim delay, suitable for use by a silicon compiler. Data-flow graphs for computational networks which use trees of operators, each performing associative and commutative combining of its respective imput operands to generate a respective output operand, are converted to data-flow graphs with multiple-input operators. Data-flow graphs with multiple-input operators, after being optimally scheduled, are converted to data-flow graphs which use trees of dual-input operators or of dual-input and three-input operators, those trees having minimum latency and shim delay associated with them. These data-flow graphs then have shim delay minimized in them, e.g. by being subjected to linear programming.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.