Mechanism providing concurrent computational/communications in SIMD architecture
US5175858A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 4, 1991 |
| Grant date | Dec 29, 1992 |
| Priority date | — |
| Expiry date | Mar 4, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17343
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A concurrent computation/communication architecture is intended for use in a single instruction stream, multiple data stream (SIMD) processor node which includes an input bus (20), an input unit (54), manipulation units (58, 60, 62, 64, 66) and an output bus (22). Processor nodes (12, 14, 16, 18) include an output unit (68) which receives data from the input unit (54) and the various manipulation units. Processor nodes (12, 14, 16, 18) store and transmit data from the output unit (68) at a selected time over the output bus (22). A processor node control unit (56) is provided for controlling the exchange of data between the processor nodes (12, 14, 16, 18), their associated output buffers (38, 40, 42, 44) and the output bus (22).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.