Personal computer memory bank parity error indicator
US5177747A · kind A · utility
14Cited by
14References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 7, 1992 |
| Grant date | Jan 5, 1993 |
| Priority date | — |
| Expiry date | Feb 7, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0772
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A personal computer has two memory banks respectively connected to two parity check units operative to detect parity errors. Upon doing so, each unit feeds a parity error signal to a separate latch. The latches are connected to a logic circuit which is in turn connected to an interrupt controller that initiates an interrupt when a parity error occurs. One latch is further connected to a check bit of a register of an I/O port and the check bit is set by the one latch. An interrupt handler reads the register and provides messages indicating which memory bank caused the parity error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.