Digital clock timing generation in a spread-spectrum digital communication system
US5177766A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 1991 |
| Grant date | Jan 5, 1993 |
| Priority date | — |
| Expiry date | Jun 3, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/707
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A unique method and system is disclosed for generating digital clock timing in a receiver for use in direct-sequence spread-spectrum digital communication systems wherein spread data is delivered from a transmitter to a receiver. The present invention provides at the transmitter frames of digital communication data with each frame having a plurality of time slots and with each time slot having a plurality of digital bits. The transmitter utilizes direct-sequence spreading codes for spreading the digital bits in the time frame. The direct sequence spreading codes each have the same fixed sequence length of M chips and, furthermore, the number of chips per bit CB to spread each digital bit is constant and fully aligned with each digital bit. The ration of M:CB is an integer and the ratio of time of each time slot to the time of the M chips also equals an integer. The spread frames of digital information are despread at the receiver with receiver provided identical direct-sequence codes. The digital clock timing is generated from the receiver's pseudo random sequence generator. Bit timing equals CB*8, nibble timing equals 4*CB, and byte timing equals CB.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.