Microprocessor information exchange with updating of messages by asynchronous processors using assigned and/or available buffers in dual port memory
US5179665A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1989 |
| Grant date | Jan 12, 1993 |
| Priority date | — |
| Expiry date | Nov 13, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/167
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Updated images of messages are passed between asynchronous digital processors using dual port shared memory. In the basic form of the invention, three buffers in shared memory are assigned to each message. Where one of the processors is a controller for a data link channel carrying n messages, 2n+1 buffers are provided in free shared memory space with 2 buffers assigned to each message at all times and a common buffer serving as the third buffer for all of the messages. Where linked buffers in local memory of a controller processor receive message updates from a data highway, two buffers in shared memory are assigned to each message and a linked buffer in the controller local memory serves as the third buffer. The buffers containing the message updates are passed between processors by use of a buffer status array in shared memory. A semaphore lock in the array permits only one processor at a time to assign or release buffers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.