Method and apparatus for predicting valid performance of virtual-address to physical-address translations
US5179674A · kind A · utility
26Cited by
3References
6Claims
0Family size
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Key dates
| Filing date | Jul 25, 1988 |
| Grant date | Jan 12, 1993 |
| Priority date | — |
| Expiry date | Jul 25, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/655
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A prediction logic device operating in conjunction with a vector processor to predict, before the completion of the translation of the virtual addresses of all of the data elements of a vector, the valid performance of all virtual-address to physical-address translations for the data elements of the vector. The prediction logic device asserts an MMOK signal to a scalar processor when it becomes known that no memory management fault and/or translation buffer miss will occur such that the scalar processor can resume vector instruction issue to the vector processor at the earliest possible time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.