Method and apparatus for current window cache with switchable address and out cache registers
US5179681A · kind A · utility
10Cited by
5References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 16, 1989 |
| Grant date | Jan 12, 1993 |
| Priority date | — |
| Expiry date | Nov 16, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor having a plurality of windowed registers comprising IN, OUT and local window registers, where the IN registers of each window are addressable as the OUT registers of a logically-adjacent succeeding window. The processor also having a cache of two sets of IN/OUT registers with switchable addresses and a set of local cache registers. The addresses of the first set of IN/OUT registers can be changed to the addresses of the second set of IN/OUT registers, and vice versa, when the current window changes during a save or restore operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.