Method and apparatus for improved current window cache with switchable address IN, OUT, and local cache registers
US5179682A · kind A · utility
8Cited by
5References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 15, 1990 |
| Grant date | Jan 12, 1993 |
| Priority date | — |
| Expiry date | May 15, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor which has a plurality of windowed registers. Each of the windowed registers comprise IN, OUT and LOCAL window registers. The IN registers of each window are addressable as the OUT registers of a logically-adjacent succeeding window. The processor also has a cache of at least four sets of cache registers with switchable addresses. Each set of cache registers is capable of holding data of the IN, OUT or LOCAL window registers. The addresses of each set of cache registers are changed to the addresses of a different set of cache registers when the current window changes during a save or restore operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.