N-byte stack-oriented CPU using a byte-selecting control for enhancing a dual-operation with an M-byte instruction word user program where M<N<2M
US5179691A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 1989 |
| Grant date | Jan 12, 1993 |
| Priority date | — |
| Expiry date | Apr 12, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3017
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for enhancing the operation of a M byte instruction word CPU when operating user programs on an N byte instruction word CPU. The M-Byte instruction word CPU is provided with an N-Byte instruction register and a main memory for supplying N-Byte instruction words or M-Byte instruction words to said N-Byte instruction register. An operational code multiplexer and an parameter code multiplexer are connectable to selective outputs of said instruction register so that any one of the M-Bytes may be selected as an operational code and any one of the remaining M-Bytes may be selected as parameter code bytes, and selection means including sequencer means are provided for operating the operational code multiplexer and the parameter code multiplexer in an M-Byte instruction word CPU mode of operation or as an N-Byte instruction word CPU mode of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.