Sorting circuit using first and last buffer memories addressed by reference axis data and chain buffer memory addressed by datum number of the first and last buffer memories
US5179717A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1989 |
| Grant date | Jan 12, 1993 |
| Priority date | — |
| Expiry date | Nov 13, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99937
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for sorting a plurality of inputted (reference-axis) data includes an index generator for generating an index (datum number) for each of the inputted data; a first buffer memory having storage areas each of which can be addressed by the data, the first buffer memory for storing an index generated by the index generator when the corresponding data is initially inputted into the index generator; a last buffer memory having storage areas each of which can be addressed by the data, the last buffer memory for updating and storing an index generated by the index generator at each time when the corresponding data is inputted thereinto; a chain buffer memory having chain index storage areas each of which can be addressed by the previous index in the chain; a first control for writing a new updated index into a chain index storage area addressed by a before-updated index at each time when the index of the last buffer memory is updated; a second control for writing the index of the data into the chain datum number storage areas so that they will be chained with each other in the ascending or descending order of the sorted data; and a third control for reading the index in the chain…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.