Power-on reset architecture
US5180926A · kind A · utility
19Cited by
3References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 26, 1991 |
| Grant date | Jan 19, 1993 |
| Priority date | — |
| Expiry date | Nov 26, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/223
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power-on reset circuit for providing a reset signal to an active device on an integrated circuit (IC). The circuit includes a RC circuit for producing a reset signal until its capacitor fully charges. The circuit also includes a voltage detector for preventing the charge from collecting on the capacitor of the RC circuit until the voltage is at a functional level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.