Parallel multiplier using skip array and modified wallace tree
US5181185A · kind A · utility
8Cited by
5References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 4, 1991 |
| Grant date | Jan 19, 1993 |
| Priority date | — |
| Expiry date | Jan 4, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3876
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel multiplier by a skip array and a modified Wallace tree utilizes a modified Booth's encoder for encoding a multiplier according to a modified Booth's algorithm, a skip array for partial products, a modified wallace tree for adding binary bits, and a hybrid prefix adder for adding the final two lines. Fast multiplication of 0 (log n) is continuously performed without a standby state of a carry output and the regularity of the arrangement of the parallel multiplier is improved so that its chip area and manufacturing cost are reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.