Method of filling a recess flat with a material by a bias ECR-CVD process
US5182221A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 12, 1991 |
| Grant date | Jan 26, 1993 |
| Priority date | — |
| Expiry date | Jun 12, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/169
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of filling a recess so that it is flat with a material by a bias ECR-CVD process is capable of depositing the recess with the material without resulting in the increase in the aspect ratio of the recess with the progress of the deposition process and without forming any voids in the material filling up the recess. A method in accordance with the present invention is characterized in that the bias ECR-CVD process is controlled so as to meet a condition expressed by: R=2y/x, where R is the deposition rate ratio, namely, the ratio of a vertical deposition rate at which the material is deposited on the vertical side surface of the recess to a deposition rate at which the material deposited on the horizontal bottom surface of the recess, x is the width of the recess and y is the depth of the recess. In another method of filling a recess flat with a material by a bias ECR-CVD process in accordance with the present invention alternately a deposition cycle using a source gas containing a silicon-containing gas and a deposition cycle using a source gas containing a silicon hydride to obviate the adverse influence of a layer of the material formed by the deposition process using the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.