Nonvolatile semiconductor memory device with reduced variation in source potential of floating gate type memory transistor and operating method therefor
US5182725A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 1991 |
| Grant date | Jan 26, 1993 |
| Priority date | — |
| Expiry date | Sep 25, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a nonvolatile semiconductor device in which source metal interconnections for coupling to ground a source of a floating gate type memory transistor are commonly provided for each predetermined plurality of memory transistors, switching transistors are provided for each column for coupling to ground columns excluding the selected column when a single column is selected in response to an external column address. Each of the switching transistors operates in response to an inverted signal of an output of a column decoder. According to this structure, a variation in source potential of each memory transistor caused by the difference in source resistance associated with each of the memory transistors is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.