Solder interconnection verification
US5184768A · kind A · utility
10Cited by
4References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 29, 1990 |
| Grant date | Feb 9, 1993 |
| Priority date | — |
| Expiry date | Nov 29, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A solder interconnection verification system is used in verifying the formation of solder joints which are hidden from view under a component (25). Solder material (28) is attached or reflow soldered to component solder pads (26). The substrate solder pads (22) have a small solderable portion (24) attached to, and extending outward from, the solder pads (22). The component is placed on the substrate (20) and reflow soldered to wet the solder (38) to the substrate solder pads (32 and 34), creating an irregularly shaped solder joint (38). The joint (38) thus formed is inspected using x-rays after reflow.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.