Method of making self-aligned gate providing improved breakdown voltage
US5185278A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 22, 1990 |
| Grant date | Feb 9, 1993 |
| Priority date | — |
| Expiry date | Oct 22, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/951
Abstract
A three level mask structure is formed on a wafer. The top layer of the mask structure has an opening that defines an etch area. The middle layer of the mask structure is etched through the opening in the top layer. This opening in the middle layer defines a gate deposition area. The layer adjacent to the wafer is etched, using the opening in the middle mask layer to define the etch area, until the etching undercuts the middle layer by a predetermined amount. The opening in the layer adjacent to the wafer is used to define an etch area on the wafer. The wafer is etched to form source and drain areas. Gate material is deposited onto the wafer using the opening in the middle layer to determine the deposition area. The mask structure is then removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.