Digital integrating clock extractor
US5185768A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 1990 |
| Grant date | Feb 9, 1993 |
| Priority date | — |
| Expiry date | Oct 9, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0338
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital integrating clock extraction technique for communication systems and information and data processing systems having high jitter and/or noise is disclosed. The technique is based on the integration and periodic analysis of a plurality of sorted data edge transitions of a received serial data stream. A retiming clock phase is selected from a plurality of locally generated clock signals of different phase. The retiming clock selection is preferably reevaluated after N data edge transition sorts. The resultant data edge histogram can be cumulative of all sorted transitions or merely cumulative of the last N sorted transitions. Corresponding methods and apparatus are described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.