Easily testable high speed digital counter
US5185769A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 15, 1991 |
| Grant date | Feb 9, 1993 |
| Priority date | — |
| Expiry date | Oct 15, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A high speed digital counter that can be easily tested comprises a plurality of subcounters having an input for receiving an incrementing signal and a carry output for outputting a carry signal when the subcounter has reached its counting capacity. The carry output of each subcounter is gated to the input of a next more significant subcounter by an OR gate which receives as inputs the carry signal and a test signal. The OR gate performs an OR on these two signals and outputs the result to the input of the next more significant subcounter. The OR gate allows the test signal to access each subcounter separately, and thus, each subcounter may be tested individually.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.