Parallel scrambler used in SONET data transmission
US5185799A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 1992 |
| Grant date | Feb 9, 1993 |
| Priority date | — |
| Expiry date | Feb 13, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03872
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data scrambler circuit which adds the SONET polynomial 1+X.sup.6 +X.sup.7 to data in a parallel format to thereby reduce circuitry clock rates to one-eighth the line rate, which reduces power consumption and simplifies timing constraints. A circuit embodiment includes a first series of flip-flops connected to generate the polynomial and a second series of flip-flops for holding the generated polynomial. To provide a relatively large window of time for looking at the data, parallel data is obtained by providing a parallel-to-parallel register at the output of a serial-to-parallel register. The parallel data is added to the held polynomial by a series of exclusive OR gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.