Process for fabricating an integrated circuit using local silicide interconnection lines
US5187122A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 26, 1991 |
| Grant date | Feb 16, 1993 |
| Priority date | — |
| Expiry date | Feb 26, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/019
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating a semiconductor device using local silicide interconnection lines make it possible to fabricate an integrated circuit having a plurality of electronic elements disposed on a semi-conductor substrate. The electronic elements are formed on the substrate such that they are grouped into a first region and a second region adjacent to the first region, each of these regions having predetermined conductivities. The first region has a layer of dielectric material disposed upon it with at least one capacitive element disposed on the dielectric layer. The capacitive element includes a first electrode layer and a second electrode layer. The second region has at least one double junction metal-insulator semi-conductor field effect transistor (MISFET) located therein. The MISFET includes at least three regions, a gate region and two active regions, a source region and a drain region. In accordance with the teachings of the present invention, a process is provided whereby one of said two active regions is electrically connected by a first local connection line to the first electrode layer of the capacitive element, a bond pad is disposed on the gate region, a source bon…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.