Configurable row decoder driver circuit
US5187394A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 1992 |
| Grant date | Feb 16, 1993 |
| Priority date | — |
| Expiry date | Jan 13, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A configurable decode circuit for decoding in a block architected SRAM. The configurable decode circuit comprising a decode circuit (10) which decodes through a process of deselection, a first buffer circuit (12) for buffering decode circuit (10), a delayed clock signal (15) for enabling first buffer circuit (12), a gated transmission means (13) for decoupling first buffer circuit from second buffer circuit (14), second buffer circuit (14) for driving capacitive loads, and a means for delaying driver output (16) for enabling gated transmission means (13). The decode circuit (10) is built for simplifying synthesis of the layout of a configurable decode circuit for varying configurations. The configurable decode optimizes performance by reducing the number of circuits in the critical delay path and minimizing capacitive loading on internal circuit nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.