Semiconductor integrated circuit of standard cell system
US5187555A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 1991 |
| Grant date | Feb 16, 1993 |
| Priority date | — |
| Expiry date | Sep 26, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/903
Abstract
Transistor elements which are not initially wired are previously arranged in no-cell regions created in part of cell array regions in a standard cell layout according to the layout design. When the circuit is changed in the standard cell layout, a desired circuit is formed in the no-cell region by using the transistor elements which are not initially wired. After the circuit change, an unnecessary circuit is made inoperative. Wiring inhibition regions for inhibiting the normal wiring in the standard cell layout are provided in order to extend the input and output terminals of the desired circuit from the no-cell region to the wiring region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.