BICMOS logic gate circuit and structures
US5189310A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 1991 |
| Grant date | Feb 23, 1993 |
| Priority date | — |
| Expiry date | Jan 15, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0136
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A novel BICMOS output buffer is taught including circuit means for firstly discharging the bases of the bipolar pull up and bipolar pull down transistors, and secondly to connect the base of an output transistor to its emitter when that output transistor is conducting, thereby insuring maximum voltage swing of the output voltage. The circuit means comprises an MOS transistor for discharging the base of an output transistor, and a depletion mode MOS transistor for connecting the base of an output transistor to its emitter. By utilizing MOS and depletion mode transistors, a significant area advantage is achieved, particularly when the MOS and depletion mode transistors are merged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.