Integrated distributed resistive-capacitive network
US5189593A · kind A · utility
13Cited by
5References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 4, 1991 |
| Grant date | Feb 23, 1993 |
| Priority date | — |
| Expiry date | Nov 4, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/66
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated-distributed-resistive-capacitive network (100) having a high dielectric electronically-tunable semiconductor integrated capacitor. The network (100) also includes a resistive layer (126) formed on the high dielectric semiconductor integrated capacitor, to provide the distributed resistance of the network (100). External contact to the resistive portion of the network (100) is provided via a plurality of contact terminals (122A and 122B) which are coupled to the resistive layer (126).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.