Integrated circuit structure analysis
US5191213A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 1991 |
| Grant date | Mar 2, 1993 |
| Priority date | — |
| Expiry date | Jul 5, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/24592
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The structure of a multilayered integrated circuit is determined by removing successive layers of the circuit. Following removal of each layer, the revealed surface is scanned by an electron beam. The intensity of backscattered or secondary electrons is detected by a first or second detector respectively. From the detected electron intensities, image processing circuitry derives a representation of the integrated circuit surface scanned. Where the surface of the integrated circuit is a flat layer of semiconductor substrate material having implanted doped areas, the surface is covered with a metallisation layer providing a Schottky barrier junction with the doped areas. Electron beam scanning of the metallisation layer induces a current at this junction which is monitored and processed to derive a representation of the outline of the doped implanted areas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.