Dual FET circuits having floating voltage bias
US5191238A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 30, 1990 |
| Grant date | Mar 2, 1993 |
| Priority date | — |
| Expiry date | Nov 30, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/691
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Prior art single FET switches suffer the disadvantage of uncertainties in the turning on and off thereof due to the high back bias voltage required. In the present system, by using a dual FET configuration, with the respective source regions of the FETs connected at a common node and a floating bias voltage source connecting the common node to the respective gate regions of the dual FET, a switching circuit which is capable of handling higher voltages and whose dB compression stays constant is provided. Since the dual FET circuit is symmetrical, depending on the polarity of the biasing voltage, the drain and the source regions are interchangeable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.