Reset gate for a phase detector in a phase-locked loop
US5191239A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 19, 1991 |
| Grant date | Mar 2, 1993 |
| Priority date | — |
| Expiry date | Dec 19, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09448
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high reliability phase-locked loop (PLL) is disclosed having a hyperactivity detection and correction circuit (HDC) to oversee the oscillator and the phase and frequency detector (PFD), and having a PFD reset gate that performs the required logic function to reset the PFD while not being vulnerable to an internal PFD race condition that plagues prior art phase-locked loop circuits. The HDC senses the oscillator control and signals an oscillator reset should the oscillator control rise to an abnormally high level above a predetermined limit while the PFD is not detecting the feedback signal. The oscillator reset signal then slowly propagates through an asymmetrical delay line and resets the oscillator control to a predetermined reset state. While the oscillator control is being reset, the HDC continues to monitor the oscillator control, and de-asserts the oscillator reset when the oscillator control drops to the predetermined reset state. The PLL circuit can then function normally to lock on to the reference signal. The HDC incorporates means to prevent an oscillator reset should the PLL lock onto a reference signal having a corresponding oscillator control greater than the predet…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.