Multiprocessor computer system with data bus and ordered and out-of-order split data transactions
US5191649A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 1990 |
| Grant date | Mar 2, 1993 |
| Priority date | — |
| Expiry date | Dec 21, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of transferring data in response to a read command in a computer system having a plurality of processors coupled to an address bus, a command bus and a data bus is described. A first processor generates and sends the read command to read a first data from a second processor. The second processor then determines with which one of (1) the first data and (2) a read response command and the first data it desires to respond to the read command. If the second processor determines to respond with the first data, then it acknowledges receipt of the read command and performs an ordered response in which the command and address buses are released and only the first data is later sent to the first processor via the data bus when available. If the second processor determines to respond with the read response command and the first data, then it acknowledges receipt of the read command and performs an out-of-order response in which the access of the command and address buses is first released and gained again by arbitration when the first data is determined to be available in the second processor. The second processor then gains the access of the data bus when the data bus is free of an…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.