IO adapter for system and IO buses having different protocols and speeds
US5191653A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 1990 |
| Grant date | Mar 2, 1993 |
| Priority date | — |
| Expiry date | Dec 28, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bi-directional bus adapter coupling a system bus, which operates at a first speed using a first protocol, and an IO bus, which operates at a second speed using a second protocol, and allowing data transfering devices on either bus to transfer data to or from devices on the other bus. The bus adapter includes a cycle generation mechanism which is responsive to data cycles from one of the buses in order to generate bus cycles needed to complete a data transfer to a device on the other bus. The bus adapter includes a synchronization mechanism for converting the plurality of data cycles generated by the cycle generation mechanism from either the first speed to the second speed or vice versa. The bus adapter includes bi-directional data path mechanism for routing data between the system and IO buses according to said protocols, such that the data path directs bytes of data to specific data lines to perform byte steering and dynamic bus sizing on the data from the system bus to the IO bus. The bus adapter also includes a bi-directional address transceiver mechanism for routing addresses between said system and said IO buses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.