Cascaded complementary phase code compressor
US5192956A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 13, 1991 |
| Grant date | Mar 9, 1993 |
| Priority date | — |
| Expiry date | Nov 13, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01S13/288
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention is a system that performs code compression in stages where each stage includes two processing paths 36 and 38. The two paths allow bidirectional crossover cascade complementary code compression reducing the number processing stages to log.sub.2 N and reducing the number of processing by a factor of N/(2 log.sub.2 N) where N is the length of the code. Each path includes a delay provided by a delay unit 44 and each path arithmetically combines the data from its own path with data from the other path. The upper path 36 uses an adder 40 while the lower path uses an adder/substracter unit 42 which adds or subtracts depending on the phase of the transmitted complementary phase code. The delay provided in each stage increases in a binary progression with the delay of the last stage being N/2. A systolic processor 68 is the preferred embodiment although the invention could be implemented in a programmable digital signal processor. The system can also be programmed to generate codes of various lengths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.