Digital phase locked loop circuit
US5193103A · kind A · utility
41Cited by
6References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 15, 1991 |
| Grant date | Mar 9, 1993 |
| Priority date | — |
| Expiry date | Jul 15, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0991
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An all-digital phase locked loop circuit is described in which a numerically controlled oscillator is driven at a multiple of a required output frequency; a counter is provided to divide the output frequency of the oscillator by the multiple; an analogue to digital converter is provided to sample an input signal having the required frequency, and the frequency of the numerically controlled oscillator provides the sampling rate of the converter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.