Method and apparatus for exception handling in pipeline processors having mismatched instruction pipeline depths
US5193158A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 1991 |
| Grant date | Mar 9, 1993 |
| Priority date | — |
| Expiry date | Oct 18, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3863
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for sequentially executing a plurality of pipelined instruction words of a program in which each instruction has independently selectable execution cycle count latencies. After the occurrence of an exception, instructions are identified which began after the instruction that caused the exception, and which have completed execution before execution of the exception provoking instruction was inhibited. Detection of an exception causes the processor to inhibit further execution of the exception provoking instruction. Pending instructions, which have yet to complete their execution prior to the inhibition of the exception provoking instruction, are similarly inhibited from further execution. Subsequently, the exception is serviced and the exception inducing instruction is restarted for re-execution in the processor. Pending instructions are subsequently re-executed in the sequence of their occurrence at the time the exception provoking instruction caused the processor to inhibit further instruction execution. Completed instructions are not re-executed. Applicable to computing systems having a plurality of processors, of either the same or different type such as flo…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.