Microprocessor system
US5193159A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jun 3, 1991 |
| Grant date | Mar 9, 1993 |
| Priority date | — |
| Expiry date | Jun 3, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3877
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When a coprocessor communicates a plurality of data items with a master processor and a memory according to a bus access cycle activated by the master processor, the coprocessor is supplied therein with information indicating a data storage position as a data transfer source or destination. The master processor and coprocessor independently monitor the number of the sequence of data transfers or the end of the sequence of data transfer operations. As a consequence, when executing a sequence of plural data transfer operations, the coprocessor need not receive a command from the master processor for each data transfer thereto. Further, it is not required for the coprocessor to indicate the end of the sequence of data transfer cycles to the master processor since the master processor can determine this on its own.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.