Fast interrupt mechanism for interrupting processors in parallel in a multiprocessor system wherein processors are assigned process ID numbers
US5193187A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 1992 |
| Grant date | Mar 9, 1993 |
| Priority date | — |
| Expiry date | Jun 10, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fast interrupt mechanism is capable of simultaneously interrupting a community of associated processors in a multiprocessor system. The fast interrupt mechanism enables the more effective debugging of software executing on a multiprocessor system by allowing all of the processors in a community associated with a parallel process to be halted within a limited number of clock cycles following a hardware exception or processor breakpoint. The fast interrupt mechanism consists of a set of registers that are used to identify associations among multiple processors, a comparison matrix that is used to select processors to be interrupted, a network of interconnections that transmit interrupt events to and from the processors, and elements in the processors that create and respond to fast interrupt events.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.