Reduce instruction set microprocessor
US5193206A · kind A · utility
34Cited by
1References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 10, 1992 |
| Grant date | Mar 9, 1993 |
| Priority date | — |
| Expiry date | Aug 10, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/223
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A LOW RISC (reduced instruction set computer) III microprocessor reduces the number of branches taken during execution of logic, functional, and symbolic programs to increase the efficiency and effectiveness of pipelined execution memory interleave, and reduces the complexity of RISC architectures. The LOW RISC III is a 40-bit, 4-stage pipelined processor which is pipelined with each stage operating synchronously in parallel. Pipeline breaks are reduced by moving partial unification and trail checking into hardware, and eliminating many short branches by conditional execution of the various instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.