Method for the making of the electrode metallizations of a transistor
US5194403A · kind A · utility
13Cited by
6References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 2, 1991 |
| Grant date | Mar 16, 1993 |
| Priority date | — |
| Expiry date | Oct 2, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The aim of the method is to prevent parasitic metallizations on the lateral walls of a raised pattern, which is used to self-align the electrode metallizations in a transistor. To this effect, a pair of semiconductor materials is introduced into the vertical pattern. These semiconductor materials react differently with respect to a pair of etching methods, so that a layer of one semiconductor material is etched to a greater extent than the other layer. The overhanging feature thus created interrupts the parasitic metallizations, if any, between the electrodes. The disclosed method can be applied to vertical structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.