Scanning circuit
US5194853A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 19, 1991 |
| Grant date | Mar 16, 1993 |
| Priority date | — |
| Expiry date | Dec 19, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A scanning circuit for successively scanning a plural number of capacitive loads comprising: a delay circuit 101 for delaying a supplied pulse signal from a previous stage in accordance with a first clock signal; a switching transistor 102 which is controlled by the first clock signal; an EXNOR circuit 103 which judges whether or not the signal generated by the delay circuit 101 is correct; a non-inverting buffer circuit 104 for reserve of the delay circuit 101; switching transistors 105 and 106 which are controlled in accordance with the signal generated by the EXNOR circuit 103; and an output buffer circuit 107 which is controlled in accordance with the first clock signal or a second clock signal. Accordingly, the scanning circuit can operate correctly even if one of the delay circuit 101 or the non-inverting buffer circuit 104 fails.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.