Apparatus and method for a synchronous, high speed, packet-switched bus
US5195089A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1990 |
| Grant date | Mar 16, 1993 |
| Priority date | — |
| Expiry date | Dec 31, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/682
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high speed, synchronous, packet-switched inter-chip bus apparatus and method for transferring data between multiple system buses and a cache controller. In the preferred embodiment, the bus connects a cache controller client within the external cache of a processor to a plurality of bus watcher clients, each of which is coupled to a separate system bus. The bus allows the cache controller to provide independent processor-side access to the cache and allows the bus watchers to handle functions related to bus-snooping. An arbiter is employed to allow the bus to be multiplexed between the bus watchers and cache controller. Flow control mechanisms are also employed to ensure that queues receiving packets or arbitration requests over the bus never overflow. A default grantee mechanism is employed to minimize the arbitration latency due to a request for the bus when the bus is idle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.