Method for fabricating semiconductor circuits
US5196233A · kind A · utility
26Cited by
8References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 18, 1989 |
| Grant date | Mar 23, 1993 |
| Priority date | — |
| Expiry date | Jan 18, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/15
Abstract
A method for fabricating a resistive load element for a semiconductor device can be used with standard semiconductor processes. A layer of second level poly is deposited and lightly doped P-type. A resist mask is used to dope selected regions of the poly layer N-type. The poly layer is then patterned to define conductors and resistive load elements. The resistive load elements are formed by back-to-back PN diodes formed at the interfaces between the P-type and N-type regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.