Method of fabricating silicon-based carriers
US5196377A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 1991 |
| Grant date | Mar 23, 1993 |
| Priority date | — |
| Expiry date | Aug 20, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Silicon is used to create multi-chip carriers for integrated circuits. The process of fabricating the carriers uses standard integrated circuit fabrication equipment. Cavities are etched into a silicon wafer, metallization or polysilicon is deposited to electrically interconnect the cavities, and integrated circuit die are placed in the cavities. Traces connecting the integrated circuits are buried in channels formed in the silicon, which can be doped and biased to provide enhanced isolation between traces as well as control over the electrical characteristics of the traces. The traces can be formed in multiple layers of material placed on the wafer to provide additional communication capacity in the carriers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.