Low-power clocking circuits
US5196743A · kind A · utility
12Cited by
9References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 12, 1990 |
| Grant date | Mar 23, 1993 |
| Priority date | — |
| Expiry date | Jan 12, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0019
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In switching a CMOS circuit comprising first and second switchable logic elements the first logic element is enabled so as to allow it to reach a steady logic state and the second logic element is not enabled until the first logic element reaches a substantially steady logic state. The current drawn by the circuit at any time is thereby reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.